UNIT - III PART-A Questions & Answers

UNIT III   2-Mark Questions and Answers

1.    Define pipelining.

                 Pipelining is a technique of decomposing  a sequential process into sub operations with each sub process being executed in a special dedicated segment that operates concurrently with all other segments.

2.    What are the steps required for a pipelined processor to process the instruction?

·         F Fetch: read the instruction from the memory

·         D Decode: decode the instruction and fetch the source operand(s)

·         E Execute: perform the operation specified by the instruction.

·         A  Access: Access the data memory.

·         W write: store the result in the destination location

3.    What are Hazards?

                A hazard is also called as hurdle.  The situations in pipelining when the next instruction cannot execute in the following clock cycle.  Stall is introduced by hazard.(Ideal Stage)

4.    State different types of hazards that can occur in pipeline.

                 The types of hazards that can occur in the pipelining were,

1.    Data hazards.

2.    Instruction hazards

3.    Structural hazards

5.    Define data hazards.

                A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in pipeline.  As a result some operations has to be delayed and the pipeline stalls.

6.    Define Control hazards.

                When the proper instruction cannot execute in the proper pipeline clocj cycle because the instruction that was fetched is not the one is needed; that is, the flow of instruction addresses is not what the pipeline expected.

7.    Define Structural hazards.

                The structural hazards is the situation when two instructions require the se of a given hardware resource at the same time.  The most common case in which this hazard may arise is access to memory.

8.    What are the classifications of data hazards?

                 Classification of data hazard: A pair of instructions can produce data hazard by referring reading or writing the same memory location.  Assume that I is executed before J. So, the hazards can be classified as,

1.    Structural hazard

2.    Data hazard

3.    Control hazard

9.    Define RAW hazard:

           Instruction _i tries to write a source operand before instruction _i reads it.

10. Define WAW hazard:

                Instruction _i tries to write a source operand before instruction _i reads it.

11. Define WAR hazard:

                 Instruction _i tries to write a source operand before instruction _i reads it.

12. How data hazard can be prevented in pipelining?

                Data hazards in the instruction pipelining can prevented by the following techniques.

a)    Operand Forwarding

b)    Software approach

13. How addressing modes affect the instruction pipelining?

                Degradation of performance is an instruction pipeline may be due to address dependency where operand address cannot be calculated without available information needed by addressing mode for e.g. An instructions with register indirect mode cannot proceed to fetch the operand if the previous instructions is loading the address into the register. Hence operand access is delayed degrading the performance of pipeline.

14. What is locality of reference?

                Many instructions in localized area of the program are executed repeatedly during some time period and the remainder of the program is accessed relatively infrequently, this is referred as locality of reference.

15. What is the need for reduced instruction chip?

·         Relatively few instruction types and addressing modes.

·         Fixed and easily decoded instruction formats

·         Fast single – cycle instruction execution

·         Hardwired rather than micro programmed control.

16. Define memory access time?

                The time that elapses between the initiation of an operation and completion of that operation, for example, the time between two successive READ operations.

17. List out Various branching technique used in micro program control unit?

a.    Bit – Oring

b.    Using Conditional variable

c.    Wide Branch Addressing

18. How the interrupt is handled during exception?

·         CPU identifies source of interrupt.

·         CPU obtains memory address of interrupt handles

·         PC and other CPU status information are saved

·         PC is loaded with address of the Interrupt handler and handling program to handle it.

19. What is meant by data path element?

                  A data path element is a unit used to operate or hold data within a processor. In the MIPS implementation, the data path elements include the instruction and data memories, the register file, the ALU, and adders.

20. What is the use of PC register?

                Program Counter(PC) is the register containing the address of the instruction in the program being executed.                

21. What are the 5 steps in MIPS instruction execution?

·         Fetch the instruction from the memory.

·         Read registers while decoding the instruction.  The regular format of MIPS instructions allows reading and decoding to occur simultaneously.

·         Execute the operation or calculate an address.

·         Access an operand in data memory.

·         Write the result into a register.

22. What is pipeline stall?

                Pipeline stall, also called bubble, is a stall initiated in order to resolve a hazard.  They can be seen elsewhere in the pipeline.

23. What is meant by branch prediction?

                Branch prediction is a method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome.

24. Define – Vectored Interrupts.

      Vectored interrupt is an interrupt in that the address to which the control is transferred by the cause of the exception.