UNIT - I ASSIGNMENT 1

ASSIGNMENT -1    

1. Consider three different processors P1, P2 and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI(Clock cycles per instruction) of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2

a) which processor has the highest performance expressed in instructions per second?

b) If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions in each processor                                                                                        [April 2018]

2. Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that i and k correspond to registers $s3 and $s5 and the base of the array save is in  $s6. What is the MIPS assembly code corresponding to this C segment?

    while (save[i] == k)

    i+=1;                                    [April 2018]

[Hint: refer text book  Patterson page 92]

3. Our favorite program runs in 10 seconds on computer A, which has a 2 GHz clock. We are trying to help a computer designer build a computer , B, which will run this program in 6 seconds. The designer has determined that a substantial increase in the clock rate possible, but this increase will affect the rest of the CPU design, causing computer B to require 1.2 times as many clock cycles as computer A for this program. What clock rate should we tell the designer to target?

[Hint: refer text book  Patterson page 34]

4. Write the MIPS code for the following C assignment code. How is this code compiled with MIPS registers?

 f = (g+h) - (i+j)

[Hint: refer text book  Patterson page 65 & 68]

5. Computer A has a clock cycle time of 250 ps and a CPI (Clock cycles per instruction) of 2.0 for some program, and computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much?

[Hint: refer text book  Patterson page 35]

6. A computer designer is trying to decide between two code sequences for a particular computer. The hardware designers have supplied the following facts

CPI (Clock cycles Per Instruction) for each instruction class
Instruction class	A	B	C
CPI	1	2	3

For a particular high-level language statement, the compiler writer is considering two code sequences that require the following instruction counts

Code sequence	Instruction counts for each instruction class
	A	B	C
1	2	1	2
2	4	1	1

Which code sequence executes fewer instructions?  Which code sequence is faster? What is the CPI for each sequence?

[Hint: refer text book  Patterson page 37]

7. A new simpler processor that has 85% of the capacitive load of the more complex older processor. Further, it has adjustable voltage so that it can reduce voltage 15% compared to processor B, which results in a 15% shrink in frequency. What is the impact on dynamic power?

[Hint: refer text book  Patterson page 41]